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E2G0146-18-11
Semiconductor MD51V65165
Semiconductor
This version: Mar. 1998 MD51V65165
4,194,304-Word 16-Bit DYNAMIC RAM : FAST PAGE MODE TYPE WITH EDO
DESCRIPTION
The MD51V65165 is a 4,194,304-word 16-bit dynamic RAM fabricated in Oki's silicon-gate CMOS technology. The MD51V65165 achieves high integration, high-speed operation, and low-power consumption because Oki manufactures the device in a quadruple-layer polysilicon/double-layer metal CMOS process. The MD51V65165 is available in a 50-pin plastic SOJ or 50-pin plastic TSOP.
FEATURES
* 4,194,304-word 16-bit configuration * Single 3.3 V power supply, 0.3 V tolerance * Input : LVTTL compatible, low input capacitance * Output : LVTTL compatible, 3-state * Refresh : RAS-only refresh : 4096 cycles/64 ms CAS before RAS refresh, hidden refresh : 4096 cycles/64 ms * Fast page mode with EDO, read modify write capability * CAS before RAS refresh, hidden refresh, RAS-only refresh capability * Package options: 50-pin 400 mil plastic SOJ (SOJ50-P-400-0.80) (Product : MD51V65165-xxJA) 50-pin 400 mil plastic TSOP (TSOPII50-P-400-0.80-1K) (Product : MD51V65165-xxTA) xx indicates speed rank.
PRODUCT FAMILY
Family MD51V65165-50 MD51V65165-60 Access Time (Max.) tRAC tAA tCAC tOEA 50 ns 25 ns 13 ns 13 ns 60 ns 30 ns 15 ns 15 ns Cycle Time Power Dissipation (Min.) Operating (Max.) Standby (Max.) 84 ns 104 ns 504 mW 432 mW 1.8 mW
1/16
Semiconductor
MD51V65165
PIN CONFIGURATION (TOP VIEW)
VCC 1 DQ1 2 DQ2 3 DQ3 4 DQ4 5 VCC 6 DQ5 7 DQ6 8 DQ7 9 DQ8 10 NC 11 VCC 12 WE 13 RAS 14 NC 15 NC 16 NC 17 NC 18 A0 19 A1 20 A2 21 A3 22 A4 23 A5 24 VCC 25 50 VSS 49 DQ16 48 DQ15 47 DQ14 46 DQ13 45 VSS 44 DQ12 43 DQ11 42 DQ10 41 DQ9 40 NC 39 VSS 38 LCAS 37 UCAS 36 OE 35 NC 34 NC 33 NC 32 A11R 31 A10R 30 A9 29 A8 28 A7 27 A6 26 VSS VCC 1 DQ1 2 DQ2 3 DQ3 4 DQ4 5 VCC 6 DQ5 7 DQ6 8 DQ7 9 DQ8 10 NC 11 VCC 12 WE 13 RAS 14 NC 15 NC 16 NC 17 NC 18 A0 19 A1 20 A2 21 A3 22 A4 23 A5 24 VCC 25 50 VSS 49 DQ16 48 DQ15 47 DQ14 46 DQ13 45 VSS 44 DQ12 43 DQ11 42 DQ10 41 DQ9 40 NC 39 VSS 38 LCAS 37 UCAS 36 OE 35 NC 34 NC 33 NC 32 A11R 31 A10R 30 A9 29 A8 28 A7 27 A6 26 VSS
50-Pin Plastic SOJ
50-Pin Plastic TSOP (K Type)
Function Address Input Row Address Strobe Lower Byte Column Address Strobe Upper Byte Column Address Strobe Data Input/Data Output Output Enable Write Enable Power Supply (3.3 V) Ground (0 V) No Connection
Pin Name A0 - A9, A10R, A11R RAS LCAS UCAS DQ1 - DQ16 OE WE VCC VSS NC
Note :
The same power supply voltage must be provided to every VCC pin, and the same GND voltage level must be provided to every VSS pin. 2/16
Semiconductor
MD51V65165
BLOCK DIAGRAM
WE
I/O Controller I/O Controller
10 8
RAS LCAS UCAS
Timing Generator
OE
Output Buffers
8
DQ1 - DQ8
8
Column Address Buffers Internal Address Counter
10
Column Decoders
Input Buffers
8
A0 - A9
10
Refresh Control Clock
Sense Amplifiers
16
I/O Selector
16
8
A10R, A11R
2
Row Row Address 12 DecoBuffers ders
Input Buffers
8
Word Drivers
Memory Cells
8
DQ9 - DQ16
Output Buffers
8
VCC
On Chip VBB Generator On Chip IVCC Generator
VSS
3/16
Semiconductor
MD51V65165
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Parameter Voltage on Any Pin Relative to VSS Short Circuit Output Current Power Dissipation Operating Temperature Storage Temperature Symbol VT IOS PD* Topr Tstg Rating -0.5 to 4.6 50 1 0 to 70 -55 to 150 Unit V mA W C C
*: Ta = 25C Recommended Operating Conditions
Parameter Power Supply Voltage Input High Voltage Input Low Voltage Symbol VCC VSS VIH VIL Min. 3.0 0 2.0 -0.3 Typ. 3.3 0 -- -- Max. 3.6 0 VCC + 0.3 0.8 (Ta = 0C to 70C) Unit V V V V
Capacitance
Parameter Input Capacitance (A0 - A9, A10R, A11R) Input Capacitance (RAS, LCAS, UCAS, WE, OE) Output Capacitance (DQ1 - DQ16) Symbol CIN1 CIN2 CI/O Typ. -- -- --
(VCC = 3.3 V 0.3 V, Ta = 25C, f = 1 MHz) Max. 5 7 7 Unit pF pF pF
4/16
Semiconductor DC Characteristics
Parameter Output High Voltage Output Low Voltage Input Leakage Current
Symbol
MD51V65165
(VCC = 3.3 V 0.3 V, Ta = 0C to 70C) Condition MD51V65165 -50 Min. VOH IOH = -2.0 mA VOL IOL = 2.0 mA 0 V VI VCC + 0.3 V; ILI All other pins not under test = 0 V DQ disable 0 V VO VCC RAS, CAS cycling, tRC = Min. RAS, CAS = VIH ICC2 RAS, CAS VCC -0.2 V RAS cycling, ICC3 CAS = VIH, tRC = Min. RAS = VIH, ICC5 CAS = VIL, DQ = enable ICC6 RAS cycling, CAS before RAS RAS = VIL, ICC7 CAS cycling, tHPC = Min. -- 140 -- 120 mA 1, 3 -- 140 -- 120 mA 1, 2 -- 5 -- 5 mA 1 -- 140 -- 120 mA 1, 2 -10 10 -10 10 mA 2.4 0 Max. VCC 0.4 MD51V65165 -60 Min. 2.4 0 Max. VCC 0.4 V V Unit Note
Output Leakage Current Average Power Supply Current (Operating) Power Supply Current (Standby) Average Power Supply Current (RAS-only Refresh) Power Supply Current (Standby) Average Power Supply Current (CAS before RAS Refresh) Average Power Supply Current (Fast Page Mode)
ILO
-10
10
-10
10
mA
ICC1
-- -- --
140 1 0.5
-- -- --
120 1 0.5
mA 1, 2
mA
1
Notes : 1. ICC Max. is specified as ICC for output open condition. 2. The address can be changed once or less while RAS = VIL. 3. The address can be changed once or less while CAS = VIH.
5/16
Semiconductor AC Characteristics (1/2)
MD51V65165
(VCC = 3.3 V 0.3 V, Ta = 0C to 70C) Note 1, 2, 3 Parameter Random Read or Write Cycle Time Read Modify Write Cycle Time Fast Page Mode Cycle Time Fast Page Mode Read Modify Write Cycle Time Access Time from RAS Access Time from CAS Access Time from Column Address Access Time from CAS Precharge Access Time from OE Output Low Impedance Time from CAS Data Output Hold After CAS Low
Symbol
MD51V65165 -50 Min. Max. -- -- -- -- 50 13 25 30 13 -- -- 13 13 13 13 50 64 -- 10,000
100,000
MD51V65165 -60 Min. 104 135 25 68 -- -- -- -- -- 0 5 0 0 0 0 1 -- 40 60 60 10 10 10 10 40 5 35 5 14 12 0 10 0 10 30 Max. -- -- -- -- 60 15 30 35 15 -- -- 15 15 15 15 50 64 -- 10,000
100,000
Unit Note ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 12 12 13 13 5 6 15 7, 8 7, 8 7 7 3 4, 5, 6 4, 5 4, 6 4, 13 4 4
tRC tRWC tHPC tHPRWC tRAC tCAC tAA tCPA tOEA tCLZ tDOH
84 110 20 58 -- -- -- -- -- 0 5 0 0 0 0 1 -- 30 50 50 7 7 7 7 35 5 30 5 11 9 0 7 0 7 25
CAS to Data Output Buffer Turn-off Delay Time tCEZ RAS to Data Output Buffer Turn-off Delay Time tREZ OE to Data Output Buffer Turn-off Delay Time tOEZ WE to Data Output Buffer Turn-off Delay Time tWEZ Transition Time Refresh Period RAS Precharge Time RAS Pulse Width RAS Hold Time RAS Hold Time referenced to OE CAS Pulse Width CAS Hold Time CAS to RAS Precharge Time RAS Hold Time from CAS Precharge OE Hold Time from CAS (DQ Disable) RAS to CAS Delay Time RAS to Column Address Delay Time Row Address Set-up Time Row Address Hold Time Column Address Set-up Time Column Address Hold Time Column Address to RAS Lead Time tT tREF tRP tRAS tRSH tROH tCAS tCSH tCRP tRHCP tCHO tRCD tRAD tASR tRAH tASC tCAH tRAL
RAS Pulse Width (Fast Page Mode with EDO) tRASP
-- -- -- 10,000 -- -- -- -- 37 25 -- -- -- -- --
-- -- -- 10,000 -- -- -- -- 45 30 -- -- -- -- --
CAS Precharge Time (Fast Page Mode with EDO) tCP
6/16
Semiconductor AC Characteristics (2/2)
MD51V65165
(VCC = 3.3 V 0.3 V, Ta = 0C to 70C) Note 1, 2, 3 Parameter Read Command Set-up Time Read Command Hold Time Read Command Hold Time referenced to RAS Write Command Set-up Time Write Command Hold Time Write Command Pulse Width WE Pulse Width (DQ Disable) OE Command Hold Time OE Precharge Time OE Command Hold Time Write Command to RAS Lead Time Write Command to CAS Lead Time Data-in Set-up Time Data-in Hold Time OE to Data-in Delay Time CAS to WE Delay Time Column Address to WE Delay Time RAS to WE Delay Time CAS Precharge WE Delay Time CAS Active Delay Time from RAS Precharge RAS to CAS Set-up Time (CAS before RAS) RAS to CAS Hold Time (CAS before RAS) WE to RAS Precharge Time (CAS before RAS) WE Hold Time from RAS (CAS before RAS)
Symbol
MD51V65165 -50 Min. Max. -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0 0 0 0 7 7 7 7 7 7 7 7 0 7 13 30 42 67 47 5 5 10 10 10
MD51V65165 -60 Min. 0 0 0 0 10 10 10 10 10 10 10 10 0 10 15 34 49 79 54 5 5 10 10 10 Max. -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
Unit Note ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 14 11, 12 11, 12 10 10 10 10 12 12 13 12 9, 12 9 10, 12 12
tRCS tRCH tRRH tWCS tWCH tWP tWPE tOEH tOEP tOCH tRWL tCWL tDS tDH tOED tCWD tAWD tRWD tCPWD tRPC tCSR tCHR tWRP tWRH
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Semiconductor Notes:
MD51V65165
1. A start-up delay of 200 s is required after power-up, followed by a minimum of eight initialization cycles (RAS-only refresh or CAS before RAS refresh) before proper device operation is achieved. 2. The AC characteristics assume tT = 2 ns. 3. VIH (Min.) and VIL (Max.) are reference levels for measuring input timing signals. Transition times (tT) are measured between VIH and VIL. 4. This parameter is measured with a load circuit equivalent to 1 TTL load and 100 pF. The output timing reference levels are VOH = 2.0 V and VOL = 0.8 V. 5. Operation within the tRCD (Max.) limit ensures that tRAC (Max.) can be met. tRCD (Max.) is specified as a reference point only. If tRCD is greater than the specified tRCD (Max.) limit, then the access time is controlled by tCAC. 6. Operation within the tRAD (Max.) limit ensures that tRAC (Max.) can be met. tRAD (Max.) is specified as a reference point only. If tRAD is greater than the specified tRAD (Max.) limit, then the access time is controlled by tAA. 7. tCEZ (Max.), tREZ (Max.), tWEZ (Max.) and tOEZ (Max.) define the time at which the output achieves the open circuit condition and are not referenced to output voltage levels. 8. tCEZ and tREZ must be satisfied for open circuit condition. 9. tRCH or tRRH must be satisfied for a read cycle. 10. tWCS, tCWD, tRWD, tAWD and tCPWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If tWCS tWCS (Min.), then the cycle is an early write cycle and the data out will remain open circuit (high impedance) throughout the entire cycle. If tCWD tCWD (Min.) , tRWD tRWD (Min.), tAWD tAWD (Min.) and tCPWD tCPWD (Min.), then the cycle is a read modify write cycle and data out will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, then the condition of the data out (at access time) is indeterminate. 11. These parameters are referenced to the UCAS and LCAS, leading edges in an early write cycle, and to the WE leading edge in an OE control write cycle, or a read modify write cycle. 12. These parameters are determined by the falling edge of either UCAS or LCAS, whichever is earlier. 13. These parameters are determined by the rising edge of either UCAS or LCAS, whichever is later. 14. tCWL should be satisfied by both UCAS and LCAS. 15. tCP is determined by the time both UCAS and LCAS are high.
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E2G0115-17-41S Semiconductor
TIMING WAVEFORM
Read Cycle
VIH - RAS VIL - tCRP VIH - CAS VIL - VIH - VIL - VIH - VIL - VIH - VIL - VOH - VOL -
tASR Address
Row
WE OE
DQ
Write Cycle (Early Write)
RAS
VIH - VIL - VIH - VIL - VIH - VIL - VIH - VIL -
tCRP CAS
tASR Address
WE
OE
VIH - VIL - VIH - VIL -
DQ
,,, , ,,,
MD51V65165
tRC tRAS tRP tCRP tCSH tRCD tRAD tRSH tCAS tRAL tRAH tASC tCAH Column tRCS tRRH tRCH tAA tROH tOEA tREZ tRAC tCAC tOEZ tCEZ Open Valid Data-out tCLZ "H" or "L" tRC tRAS tRP tCRP tCSH tRCD tRSH tRAD tRAH tCAS tASC tCAH tRAL Row Column tWCS tWCH tWP tCWL tRWL tDS tDH Valid Data-in Open "H" or "L"
9/16
Semiconductor Read Modify Write Cycle
tRWC tRAS VIH - RAS VIL - tCRP CAS VIH - VIL - tASR Address VIH - VIL - VIH - VIL - VIH - VIL - tRAC DQ VI/OH- VI/OL- tCLZ tRAH tASC tCAH Column tRAD tAA tRCS tOEA tOED tCAC tOEZ Valid Data-out tDS tOEH tDH Valid Data-in tRWD tCWD tAWD tRCD
MD51V65165
tRP tCRP tRSH tCAS
tCSH
Row
WE OE
tCWL tRWL tWP
,
"H" or "L"
10/16
Semiconductor
Fast Page Mode Read Cycle (Part-1)
RAS
VIH - VIL -
CAS
VIH - VIL -
Address
VIH - VIL - VIH - VIL - VIH - VIL -
WE
OE
,,,,
MD51V65165
tRASP tRP tRHCP tCRP tRCD tHPC tCP tCP tCAS tCAS tCAS tRAD tASR tRAH tASC tCSH tCAH tASC tCAH tASC tCAH Column Row Column Column tRCS tRRH tCHO tOCH tRAC tAA tOEP tAA tAA tOEP tOEA tCAC tCPA tDOH
Valid Data-out
tCAC
Valid Data-out
tOEA
tOEA
tOEZ
tCAC
Valid* Data-out
tOEZ
Valid* Data-out
tREZ
DQ
VOH - VOL -
tCLZ
* : Same Data,
"H" or "L"
Fast Page Mode Read Cycle (Part-2)
tRASP RAS VIH - VIL - tCRP CAS VIH VIL - - tASR Address VIH - VIL - VIH - VIL - VIH - VIL - Row tRCD tCP tCAS tRHCP tHPC tCP tRP tCRP
tRAD tRAH
WE
OE
DQ
VOH - VOL -
,,
tCAS tCAS tCSH tASC tCAH Column tASC tCAH tASC tCAH Column Column tRCS tRCS tRAC tAA tRCH tWPE tAA tAA tCPA tOEA tCAC tCAC tWEZ tCAC tDOH tCEZ tCLZ
Valid Data-out Valid Data-out Valid Data-out
"H" or "L"
11/16
Semiconductor
Fast Page Mode Write Cycle (Early Write)
RAS
VIH - VIL -
CAS
VIH - VIL -
Address
VIH - VIL - VIH - VIL - VIH - VIL - VIH - VIL -
WE
OE
DQ
Fast Page Mode Read Modify Write Cycle
RAS
VIH - VIL -
tCRP CAS VIH - VIL - tASR Address VIH - VIL -
WE
VIH - VIL -
OE
VIH - VIL -
DQ
VI/OH - VI/OL -
,,, , ,
MD51V65165
tRASP tRP tCRP tRCD tHPC tHPC tCP tCP tCAS tCAS tCAS tRAD tASR tRAH tCSH tASC tCAH Column tASC tCAH tASC tRSH tCAH Row Column Column tWCS tWCH tWCS tWCH tWCS tWCH tDS tDH tDS tDH tDS tDH Valid Data-in Valid Data-in Valid Data-in "H" or "L"
tRASP
tRWD
tRCD
tCP
tRAD
tCWD
tRAH tASC
tHPRWC
tCPWD tASC
tCAH
tCWL
tCPA tCAH
tRWL
Row
Column
Column
tRCS
tAWD
tRCS
tCWD
tRAC
tAWD
tAA
tDS tWP
tAA
tDS
tWP
tOEA
tOED
tOEH tDH
tOEA
tOED
tOEH tDH
tCAC
tOEZ
tCAC
tOEZ
Valid Data-out
Valid Data-in
Valid Data-out
Valid Data-in
tCLZ
tCLZ
"H" or "L"
12/16
Semiconductor
e
RAS-Only Refresh Cycle
tRC RAS VIH - VIL - tRAS tRP tCRP tRPC CAS VIH - VIL - tASR tRAH Address VIH - VIL - Row tCEZ DQ VOH - VOL - Open Note: WE, OE = "H" or "L"
,
MD51V65165
"H" or "L"
CAS before RAS Refresh Cycle
t RP
tRC
tRAS
tRP
RAS
VIH - VIL -
t RPC
tRPC
tCP
tCSR
tCHR
CAS
VIH - VIL -
tWRP
tWRH
tWRP
WE
VIH - VIL - VOH - VOL -
t CEZ
DQ
Open
Note: OE, Address = "H" or "L"
"H" or "L"
13/16
Semiconductor Hidden Refresh Read Cycle
MD51V65165
RAS
CAS
Address
WE
OE
DQ
Hidden Refresh Write Cycle
RAS
CAS
Address
WE
OE
,, , , ,, , ,,
tRC tRAS tRP tRC tRAS tRP VIH - VIL - VIH - VIL - VIH - VIL - VIH - VIL - tCRP tRCD tRSH tCHR tASR tRAH tRAD tASC tCAH Row Column tRCS tRAL tRRH tAA tROH VIH - VIL - tOEA tWRP tWRH tRAC tCAC tCLZ tCEZ tOEZ tREZ VOH - VOL - Open Valid Data-out "H" or "L"
tRC tRAS tRP tRC tRAS tRP VIH - VIL - VIH - VIL - tCRP tRCD tRSH tCHR tASR tRAH tRAD tASC tCAH tRAL VIH - VIL - VIH - VIL - VIH - VIL - VIH - VIL -
Row
Column
tWCS
tRWL tWCH
tWP
tDS
tDH
DQ
Valid Data-in "H" or "L"
14/16
Semiconductor
MD51V65165
PACKAGE DIMENSIONS
(Unit : mm)
SOJ50-P-400-0.80
Mirror finish
Package material Lead frame material Pin treatment Solder plate thickness Package weight (g)
Epoxy resin 42 alloy Solder plating 5 mm or more TYP.
Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
15/16
Semiconductor
MD51V65165
(Unit : mm)
TSOPII50-P-400-0.80-1K
Mirror finish
Package material Lead frame material Pin treatment Solder plate thickness Package weight (g)
Epoxy resin 42 alloy Solder plating 5 mm or more 0.61 TYP.
Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
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